set to the reference frequency while the new frequency set-Therefore: tles P’ = P − 3 = 91 − 3 = 88 = 1011000 Control word = 0 1 1 1 1 0 0 0 0 0 X 1 0...

Ludzie pragną czasami się rozstawać, żeby móc tęsknić, czekać i cieszyć się z powrotem.

Data
The programming word, W, is generated by first creating the 4. Wait for VCO to settle in the new state (10 ms to within 0.1%
non-bit-stuffed word W’ by concatenating P’=1011000, D=1, of the new frequency).
M=001, Q’=0011111, I=0000, and then bit-stuffing.
Load the Control register to enable new frequency output.
W’ = 1011000 1 001 0011111 0000
The transition is guaranteed to be glitch-free. (See the tim-W = 10110001001001101110000
ing specifications.)
Zeros were stuffed in one place in this example.
Control word = 0 1 1 1 1 0
0 0 0 0 X 0 0 0
Protocol Word
Control Reg. Data
4

ICD2053B
Maximum Ratings
Static Discharge Voltage ......................................... Class 1[3]
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-lines, not tested.)
Operating Range
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Ambient
Input Voltage ................................................... −0.5V to VDD+0.5
Range
Temperature
VDD
Operating Temperature ......................................0°C to +70°C
Commercial
0°C to +70°C
5V ± 10%
Storage Temperature ....................................... −65°C to +150°C
Note:
3.
Static sensitive <2000V.
Max. Soldering Temperature (10 sec) ..................... +260°C
Junction Temperature ............................................... +125°C
Operating Conditions
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
4.5
5.5
V
TA
Ambient Operating Temperature
0
70
°C
CL
Load Capacitance
25
pF
Electrical Characteristics Over the Operating Range Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH
HIGH-level Output Voltage
IOH = −4.0 mA
2.4
V
VOL
LOW-level Output Voltage
IOL = 4.0 mA
0.4
V
VIH
HIGH-level Input Voltage
Except XTALIN pins
2.0
V
VIL
LOW-level Input Voltage
Except XTALIN pins
0.8
V
V
−
IH
HIGH-level Reference Input Voltage, when
XTALIN pin only
VDD 0.8
V
DC coupled[4]
VIL
LOW-level Reference Input Voltage, when
XTALIN pin only
0.8
V
DC coupled[4]
IIH
Input HIGH Current
VIN = 5.0V, except SCLK
100
µA
IIL
Input LOW Current
VIN = 0.5V, except SCLK
−250
µA
IIH
Input HIGH Current
VIN = 5.0V, SCLK only
250
µA
IIL
Input LOW Current
VIN = 0.5V, SCLK only
−100
µA
IOZ
Output Leakage Current
Three-state
10
µA
IDD
Power Supply Current
VDD=VDD max., 100 MHz,
13
50
mA
VIN=VDD or 0V
Capacitance
Parameter
Description
Max.
Unit
CIN
Input Capacitance, except XTALIN pin
10
pF
CIN
Input Capacitance, XTALIN pin
34
pF
Switching Characteristics Over the Operating Range Parameter
Name
Description
Min.
Max.
Unit
f(REF)
Reference Frequency
Reference Oscillator nominal value[4]
1
25
MHz
t(REF)
Reference Clock Period
t(REF) = 1/f(REF)
40
1000
ns
t1
Reference Clock HIGH
Input pulse width HIGH for reference. Measured at 16
ns
Time
VDD/2, DC coupled.[4]
Note:
4.
See Externally Driven Crystal Oscillator section of the “Crystal Oscillator Topics” Application Note. For AC coupling, use an input duty cycle near 50%.
5

ICD2053B
Switching Characteristics Over the Operating Range (continued) Parameter
Name
Description
Min.
Max.
Unit
t2
Output Period
CLKOUT period (frequency), TTL levels
10 (100
2560
ns
MHz)
(391 kHz)
CLKOUT period (frequency), CMOS levels
11.1 (90
2560
MHz)
(391 kHz)
t3
Output Duty Cycle (t0/t2)
Duty cycle of CLKOUT
f(OUT) < 50 MHz AND
45%
55%
measured at 1.4V (TTL)
post-divide > 2
threshold
f(OUT) > 50 MHz OR
40%
60%
post-divide = 1
Duty cycle of CLKOUT
post-divide > 2
45%
55%
measured at VDD/2 (CMOS)
post-divide = 1
40%
60%
threshold
t4
Rise Time
Rise time for the clock output TTL 0.4V to 2.4V
3
ns
into a 25 pF load
CMOS, 0.1VDD to
6
0.9VDD
t5
Fall Time
Fall time for the clock output TTL 0.4V to 2.4V
3
ns
into a 25 pF load
CMOS, 0.1VDD to
6
0.9VDD
t6
SCLK HIGH Time
Minimum HIGH time for the SCLK clock
450
ns
t7
Clock Valid
Time required for the CLKOUT oscillator to become
t(REF)
3 * t(REF)
ns
valid after last SCLK clock[5]
+ 25
t8
Serial Data Set-up
Time required for the data to be valid prior to the 15
ns
rising edge of SCLK
t9
Hold
Time required for the data to remain valid after the 0
ns
rising edge of SCLK
t10
Delay, MUXREF[6] Asserted Time for CLKOUT to go HIGH after assertion of 0
told + 25
ns
to CLKOUT HIGH
MUXREF[6]
t11
Transition, f(OLD) to f(REF)
Delay of first falling edge of f(REF) signal at output t13
t(REF) + 25
ns
t12
Reference Output High
Output during MUXREF[6], reference DC coupled
t16 − 10
t16 + 10
ns
Time
t13
Reference Output Low
Output during MUXREF[6], reference DC coupled
t1 − 10
t1 + 10
ns
Time
t14
Transition, f(REF) to f(NEW)
Time for CLKOUT to go HIGH after release of
0
t(REF) + 25
ns
MUXREF[6]
t15
Transition, MUXREF[6] re-
Delay of first falling edge of f(NEW) signal at output tnew/2
tnew * 3/2 +
ns
leased to CLKOUT LOW
25
t16
Reference Clock Low Time Input pulse width low for reference. Measured at 18
ns
VDD/2, DC coupled[4]
t17
Reference Input Rise/Fall
Rise/fall time for DC coupled reference input[4]
t(REF)/10
ns
t18
Output Enable Delay
Delay from Output Enable HIGH to Output Valid
0
20
ns
t19
Output Disable Delay