–1 0 +1 dB Max Gain (1023)2 32 33 34 dB BLACK LEVEL CLAMP Clamp Level (Selected through Serial Interface...

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5
16
ns
Output Hold Time (tHOLD)
6
ns
ADCCLK, SHP, SHD Clock Period
47
55.6
ns
ADCCLK High-Level/Low-Level
20
28
ns
SHP, SHD Minimum Pulsewidth
10
14
ns
SHP Rising Edge to SHD Rising Edge
20
28
ns
NOTES
1Input signal characteristics defined as follows: 500mV TYP
RESET
TRANSIENT

1V MAX
200mV MAX
INPUT
OPTICAL
SIGNAL RANGE
BLACK PIXEL
2Use equations on page 8 to calculate gain.
3SNR = 20 log10 (Full-Scale Voltage/RMS Output Noise).
420 pF loading; timing shown in Figure 1.
5Internal aperture delay for actual sampling edge.
Specifications subject to change without notice.
REV. 0
–3–
AD9806–SPECIFICATIONS
AUX-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
Normal (D-Reg 00)
50
mW
High-Speed (D-Reg 01)
95
mW
MAXIMUM CLOCK RATE
Normal (D-Reg 00)
18
MHz
High-Speed (D-Reg 01)
28.6
MHz
PGA (Gain Selected through Serial Interface F-Reg) Max Input Range
700
mV p-p
Max Output Range
1000
mV p-p
Gain Control Resolution
7
Bits
Gain Range
Min Gain (Code 128)
–2
dB
Max Gain (Code 255)
15
dB
ACTIVE CLAMP
Clamp Level (Selected through Serial Interface E-Reg) CLP0 (E-Reg 00)
32
LSB
CLP1 (E-Reg 01)
48
LSB
CLP2 (E-Reg 10)
64
LSB
CLP3 (E-Reg 11)
16
LSB
TIMING SPECIFICATIONS1
Pipeline Delay
9
Cycles
Internal Clock Delay (tID)
Output Delay (tOD)
14.5
16
ns
Output Hold Time (tHOLD)
7
ns
NOTES
120 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
AUXMID-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
50
mW
MAXIMUM CLOCK RATE
18
MHz
PGA (Gain Selected through Serial Interface F-Reg) Max Input Range
700
mV p-p
Max Output Range
1000
mV p-p
Gain Control Resolution
9
Bits
Gain Range (See Figure 5b for Gain Curve) Min Gain (Code 512)
–4
dB
Max Gain (Code 1023)
14
dB
MIDSCALE OFFSET LEVEL (AT MAX PGA GAIN) 462
512
562
LSB
TIMING SPECIFICATIONS1
Pipeline Delay
9
Cycles
Internal Clock Delay (tID)
Output Delay (tOD)
14.5
16
ns
Output Hold Time (tHOLD)
7
ns
NOTES
120 pF loading; timing shown in Figure 2.
Specifications subject to change without notice.
–4–
REV. 0
AD9806
ADC-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Parameter
Min
Typ
Max
Unit
POWER CONSUMPTION
(Same as AUX-MODE)
MAXIMUM CLOCK RATE
(Same as AUX-MODE)
ACTIVE CLAMP
(Same as AUX-MODE)
TIMING SPECIFICATIONS1
(Same as AUX-MODE)
Specifications subject to change without notice.
DAC SPECIFICATIONS (DAC1 and DAC2) Parameter
Min
Typ
Max
Unit
RESOLUTION
8
Bits
MIN OUTPUT
0.1
V
MAX OUTPUT
VDD – 0.1
V
MAX CURRENT LOAD
1
mA
MAX CAPACITIVE LOAD
500
pF
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
Parameter
With Respect To
Min
Max
Unit
AVDD1, AVDD2
AVSS
–0.3
+3.9
V
DVDD1, DVDD2
DVSS
–0.3
+3.9
V
DRVDD
DRVSS
–0.3
+3.9
V
Digital Outputs
DRVSS
–0.3
DRVDD + 0.3
V
SHP, SHD, DATACLK
DVSS
–0.3
DVDD + 0.3
V
CLPOB, CLPDM, PBLK
DVSS
–0.3
DVDD + 0.3
V
SCK, SL, SDATA
DVSS
–0.3
DVDD + 0.3
V
VRT, VRB, CMLEVEL
AVSS
–0.3
AVDD + 0.3
V
CCDIN, CLPOUT, CLPREF, CLPBYP
AVSS
–0.3
AVDD + 0.3
V
Junction Temperature
150
°C
Lead Temperature (10 sec)
300
°C
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9806KST
–20°C to +85°C
Thin Plastic Quad Flatpack (LQFP)
ST-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 92°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although WARNING!