2000 Philips Semiconductors handbook, full pagewidth Lo Jan w-cost stereo filter...

Strona startowa Ludzie pragną czasami się rozstawać, żeby móc tęsknić, czekać i cieszyć się z powrotem.Do obszaru zarządzania wiedzą należą też problemy ochrony własności wiadomo- ści (Yan Xianglin, Zhang Yaxi 2000: 143–148) lub (szerzej) problemy...Prawdę powiedziawszy, pozbyłbym się Kane'a ze statku równie chętnie jak wszyscy...31Niektórzy sprowadzają bogactwo uczuć pozytywnych do dwóch wyrażeń - lu˝bię cię i kocham cię, przy czym obawiają się, że pierwsze może być nie˝bezpiecznie...By myœl tĂŞ równieÂż móc w sobie intensywnie odczuĂŚ, naleÂży przeÂżyĂŚ jÂą, rozpamiĂŞtywaĂŚ w spokoju, nie dopuszczajÂąc przy tym myœli innych, które by temu...pozytywizmu równiez nie wynikal probabilizm, gloszacy, ze twierdzenia moga byc tylko prawdopodobne - bo wlasnie nauka stwierdza prawa zupelnie niewatpliwe...37Moją przewagą było zaskoczenie...W ten oto sposób dowiedzieliśmy się więcej o zagadce rodu von Lipowów... 
 

Ludzie pragną czasami się rozstawać, żeby móc tęsknić, czekać i cieszyć się z powrotem.

3 Serial interface; input format I2S-bus.
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
9
L3 INTERFACE DESCRIPTION
Data transfer can only be in one direction, consisting of input to the UDA1320ATS/N2 to program sound
9.1
The L3 interface
processing and other functional features.
The following system and digital sound processing
Data bits 7 to 2 represent a 6-bit device address, bit 7
features can be controlled in the microcontroller mode of being the MSB. The address of the UDA1320ATS/N2 is
the UDA1320ATS/N2:
000101 (bit 7 to bit 2). If the UDA1320ATS/N2 receives a
• System clock frequency
different address, it will deselect its microcontroller
• Data input format
interface logic.
• De-emphasis for 32 kHz, 44.1 kHz and 48 kHz
9.2
Data transfer mode
• Volume
•
The selected address remains active during subsequent
Soft mute.
data transfers until the UDA1320ATS/N2 receives a new
The exchange of data and control information between the address command. The fundamental timing of data
microcontroller and the UDA1320ATS/N2 is accomplished
transfers is essentially the same as in the address mode, through a serial hardware interface comprising the
see Fig.6. The maximum input clock and data rate is 64 fs.
following pins:
All transfers are by 8-bit bytes. Data will be stored in the
• L3DATA
UDA1320ATS/N2 after reception of a complete byte. See
•
Fig.5 for a multi-byte transfer.
L3MODE
• L3CLOCK.
Table 4
Selection of data transfer
Information transfer through the microcontroller bus is BIT 1
BIT 0
TRANSFER
organized in accordance with the L3 format, in which two 0
0
DATA (volume, de-emphasis, mute)
different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 6).
0
1
not used
1
0
STATUS (system clock frequency,
The address mode is required to select a device
data input format)
communicating via the L3 bus and to define the
destination registers for the data transfer mode.
1
1
not used
handbook, full pagewidth
L3MODE
t
t
h(L3)A
su(L3)A
tCLK(L3)L
t
t
CLK(L3)H
su(L3)A
t h(L3)A
L3CLCK
Tcy(CLK)(L3)
t
t
su(L3)DA
h(L3)DA
L3DATA
BIT 0
BIT 7
MBK072
Fig.4 Timing address mode.
2000 Jan 10
8
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
tstp(L3)
handbook, full pagewidth
L3MODE
L3CLK
L3DATA
address
data byte #1
data byte #2
address
MBK074
Fig.5 Multi-byte transfer.
tstp(L3)
tstp(L3)
handbook, full pagewidth
L3MODE
tCLK(L3)L
t
T
h(L3)D
cy(CLK)L3
tsu(L3)D
tCLK(L3)H
L3CLCK
th(L3)DA
tsu(L3)DA
th(L3)DA
L3DATA
BIT 0
BIT 7
write
MBK073
Fig.6 Timing for data transfer mode.
The sound feature values are stored in independent
the settings that can be controlled using ‘DATA’ transfer registers. The first selection of the registers is achieved by are given in table 6.
the choice of data type that is transferred (‘STATUS’ or The second selection is performed by the 2 MSBs of the
‘DATA’ transfer). This is performed in the address mode data byte (bit 7 and bit 6). The other bits in the data byte using bit 1 and bit 0, see Table 4,. The settings that can be (bit 5 to bit 0) is the value that is placed in the selected controlled with ‘STATUS’ transfer are given in table 5, and registers.
2000 Jan 10
9
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
Table 5
Data transfer of type ‘status’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
0
SC1
SC0
IF2
IF1
IF0
0
System Clock frequency (1 : 0);
data Input Format (2 : 0)
1
0
0
0
0
0
0
0
reserved
Table 6
Data transfer of type ‘data’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
0
VC5
VC4
VC3
VC2
VC1
VC0
Volume Control (5 : 0)
0
1
0
0
0
0
0
0
reserved
1
0
0
DE1
DE0
MT
0
0
DE-emphasis (1 : 0); MuTe
1
1
0
0
0
0
0
1
default setting
9.3
Programming the features
Volume control: a 6-bit value to program the volume attenuation (VC5 to VC0), 0 to −∞ dB in steps of 1 dB.
When the data transfer of type ‘STATUS’ is selected, the features SYSTEM CLOCK FREQUENCY and DATA
Table 9
Volume settings
INPUT FORMAT can be controlled.
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME (dB)
System clock frequency: a 2-bit value to select the used external clock frequency.
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Table 7
System clock settings
0